PIC16F785-I/ML【PDF 22/206 页】IC PIC MCU FLASH 2KX14 20QFN

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118

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

Tn). The clkTn can be generated from an external or internal clock source,

selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the

timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of

whether clk

Tn is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OCnx. For more details about advanced counting

sequences and waveform generation, see ”Modes of Operation” on page 124.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by

the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

16.7

Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded. The

small “n” in register and bit names indicates the Timer/Counter number.

Figure 16-3. Input Capture unit block diagram.

When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively

on the Analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

ICFn (Int.Req.)

Analog

Comparator

WRITE

ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

ACIC*

ICNC

ICES

ACO*

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